(a) Field of the Invention
The present invention relates to a semiconductor package having a cap member and, more particularly, to a semiconductor package having a cap member for closing the opening of the semiconductor package to encapsulate a semiconductor chip in a cavity. The present invention also relates to a method for manufacturing such a semiconductor package.
(b) Description of the Related Art
A typical semiconductor package includes a wiring board or a lead frame having thereon wiring patterns and mounting thereon a semiconductor chip, which is encapsulated by a mold package on the wiring board or lead frame. In such a semiconductor package, epoxy resin having a higher dielectric constant increases the parasitic capacitance of the semiconductor chip to degrade the frequency characteristics thereof if the epoxy resin resides in close contact with the semiconductor chip. This may be avoided by an air cavity formed on the wiring board to receive therein the semiconductor chip, as described in JP-A-2000-286354, for example.
FIG. 1 shows the semiconductor package described in the above publication, wherein a wall member 32 having a top opening is fixed onto a wiring board 31 to form a package substrate defining a cavity 33, in which a semiconductor chip 37 is received. A planar cap member 35 is adhered onto the wall substrate 32 by an adhesive layer 42 at the top opening thereof for encapsulating the semiconductor chip 37 in a cavity 33. The bonding pads of the semiconductor chip 37 are connected through the bonding wires 39 and the wiring patterns of the wiring board 31 to the external terminals 40.
For fabrication of the semiconductor package shown in FIG. 1, a plurality of semiconductor packages arranged in a package array are first formed by bonding a cap substrate including a plurality of cap members 35 onto a wall substrate having a plurality of wall members 32, and then separated from one another at scribe lines by using a dicing blade.
FIG. 2 shows the package array in a top plan view thereof before bonding the cap substrate 35 onto the wall substrate 32. The semiconductor packages are substantially of a square and arranged in a two dimensional array, having a square hole 45 at each corner of the semiconductor package. The square hole 45 is used as a gas exhaustion hole from the cavity 33. Semiconductor packages are separated at the scribe lines 41 after bonding the cap substrate 35 onto the wall substrate 32 of the package substrate.
FIG. 3 shows the semiconductor packages in a sectional view thereof taken along line III—III in FIG. 2. A semiconductor chip 37 is received in the cavity 33 for which a gas exhaustion hole 45 is provided between adjacent cavities 33.
FIG. 4 shows the semiconductor packages shown in FIG. 3 in combination with the cap substrate 35, which encapsulates the plurality of semiconductor chips 37 within the respective cavities 33. For fabrication of the structure shown in FIG. 4, an adhesive layer 42 is formed on top of the wall substrate 32 before the cap substrate 35 is placed on the top of the wall substrate 32, followed by thermally curing the adhesive layer 42 to encapsulate the semiconductor chip 37 together with the air inside the cavities 33, and by dicing these substrates at the scribe lines 41.
The conventional process for fabricating the semiconductor packages as described above have the following problems. First, during heating the curable resin used as the adhesive layer 42, the air within the cavity 33 is expanded in volume to sometime flow toward outside the cavity 33 while raising the cap substrate 35. This involves a defect in adhesion between the cap substrate 35 and the wall substrate 32, thereby degrading the airtight of the cavity 33 and resistance of the semiconductor package against ingress of water.
Second, if the substrate 31, 32 or 35 has a deformation such as caused by warp, uniform adhesion is difficult to achieve. In such a case, a thrust pressure is often applied to the cap substrate 35 etc. This may cause a mechanical damage in the substrate 31, 32 or 35, thereby lowering the product yield of the semiconductor packages.